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Cognitive Information Processing, Elba Island : Italie (2010)
Memory-efficient FFT architecture using R-LFSR based CORDIC common operator
Hongzhi Wang 1, Yves Louët 1, Jacques Palicot 1, Laurent Alaus 1, Dominique Noguet 2
(06/2010)

In the Software Defined Radio (SDR) area, parameterization is becoming a very important topic in the design of multi-standard terminals. In this context, the Common Operator (CO) technique [1] defines an open and optimized terminal based on a limited set of generic components called Common Operators. The method was already described in [1] and a new relevant possible CO was presented: R-LFSR based CORDIC which is a result of synergy study between CORDIC [2] and Reconfigurable LFSR [3]. We present in this work an original FFT architecture based on the CORDIC in which R-LFSR is exploited. In this case, FFT functions which were performed by CORDIC can be performed by R-LFSR and vice-versa. The novel FFT architecture was successfully implemented on a FPGA Virtex-4 to compare with a FFT using conventional CORDIC. The complexity evaluation is presented. In the Software Defined Radio (SDR) area, parameterization is becoming a very important topic in the design of multi-standard terminals. In this context, the Common Operator (CO) technique defines an open and optimized terminal based on a limited set of generic components called Common Operators. The Method was already described in and two relevant possible CO were presented: CORDIC and Reconfigurable LFSR . Actually, CORDIC could be parameterized for matrix inversion, filters, FFT and LFSR for Gold Sequences Generators, Convolutional Coding (NSC (Non Systematic Coder), RSC(Recursive Systematic Coder) k/n), Cyclic coding, etc. In the proposed study, the synergy between CORDIC and LFSR is introduced. We present an original CORDIC architecture based on a new Reconfigurable-LFSR (RLFSR). In this case, the functions which were performed by CORDIC can be performed by R-LFSR and vice-versa. The new CORDIC architecture was successfully implemented on a FPGA Virtex-4 to compare with a classical CORDIC. The complexity evaluation is presented.
1 :  Institut d'Electronique et de Télécommunications de Rennes (IETR)
CNRS : UMR6164 – Université de Rennes 1 – Institut National des Sciences Appliquées (INSA) - Rennes – SUPELEC
2 :  Laboratoire d'Electronique et des Technologies de l'Information (LETI)
CEA : DRT/LETI
SCEE - Equipe Signal, Communication et Electronique Embarquée
Sciences de l'ingénieur/Traitement du signal et de l'image

Informatique/Traitement du signal et de l'image