| HAL: hal-00658911, version 1 |
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| FPT'11, New Dehli : Inde (2011) |
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| FPGA Implementation of Reconfigurable ADPLL Network for Distributed Clock Generation |
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| Chuan Shan 1E. Zianbetov 1 |
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| (2011) |
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| 1: | Laboratoire d'Informatique de Paris 6 (LIP6) |
| CNRS : UMR7606 – Université Pierre et Marie Curie [UPMC] - Paris VI | |
| 2: | Equipes Traitement de l'Information et Systèmes (ETIS) |
| CNRS : UMR8051 – ENSEA – Université de Cergy Pontoise | |
| 3: | Laboratoire d'Electronique et des Technologies de l'Information (LETI) |
| CEA : DRT/LETI | |
| 4: | Supélec Sciences des Systèmes - EA4454 (E3S) |
| SUPELEC | |
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| SSE - Département Signaux et Systèmes Electroniques |
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| Subject | : | Computer Science/Signal and Image Processing Engineering Sciences/Signal and Image processing Engineering Sciences/Electronics |
| hal-00658911, version 1 | |
| http://hal-supelec.archives-ouvertes.fr/hal-00658911 | |
| oai:hal-supelec.archives-ouvertes.fr:hal-00658911 | |
| From: Karine El Rassi | |
| Submitted on: Wednesday, 11 January 2012 15:39:58 | |
| Updated on: Thursday, 12 January 2012 11:46:40 | |