Plasma etching challenges involved in gate stack patterning for 45 nm technological nodes and beyond

O. R. Joubert (1) , E. Pargon (1) , G. Cunge (1) , T. Chevolleau (1) , B. Pelissier (1) , L. Vallier (1) , F. Sidor , J. Thiault (1) , R. Ramos (1) , O. Luere , E. Sungauer (1) , M. Martin (1) , X. Mellhaoui , S. Barnola , J. Foucher , T. Morel , T. Lill , A. Patterson

1 LTM - Laboratoire des technologies de la microélectronique

Domaines: Sciences de l'ingénieur [physics]

O. R. Joubert, E. Pargon, G. Cunge, T. Chevolleau, B. Pelissier, et al.. Plasma etching challenges involved in gate stack patterning for 45 nm technological nodes and beyond. 1st workshop on plasma etch and strip in microelectronic (PESM), 2007, Louvain, Belgium. ⟨hal-00397771⟩