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Communication Dans Un Congrès Année : 2007

Chamber walls coating during patterning of dielectric damascene structures with a metal hard mask: consequence on cleaning strategies

Résumé

The impact of a metal hard mask on the coating formed on the chamber walls during the dielectric etching process and reactor dry cleaning procedure has been investigated. We have used a technique based on X-ray photoelectron spectroscopy (XPS) to monitor the chemical composition of the layer deposited on an electrically floating sample placed on the top of a patterned wafer exposed to typical plasma processing conditions (coatings deposited on the floating sample are representative of those deposited on the chamber walls). We have patterned porous SiOCH damascene structures using a TiN hard mask. After hard mask opening and ashing in a silicon etcher using Cl2 based plasmas, we have shown that the chamber walls are coated by a thin and mixed SiO-TiO deposit. During low-k etching in an oxide etcher with fluorocarbon based chemistries, the chamber walls are coated by a fluorocarbon layer containing a significant concentration of Ti. We have developed a two step cleaning procedure to remove the coating formed on the chamber walls of the silicon and oxide etchers
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Dates et versions

hal-00461598 , version 1 (13-12-2022)

Identifiants

  • HAL Id : hal-00461598 , version 1

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Thierry Chevolleau, Maxime Darnon, Thibaut David, Nicolas Possémé, Olivier Joubert. Chamber walls coating during patterning of dielectric damascene structures with a metal hard mask: consequence on cleaning strategies. Plasma Etch and Strip in Microelectronics Workshop, 2007, Detroit, United States. ⟨hal-00461598⟩
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