Gate Etching for ULSI Technology : Critical Dimension Control in the sub 0.1 µm regime
Résumé
In a CMOS process, gate etching is still one of the hottest topic since the accuracy required in gate dimension control is more and more severe. Today, a gate etch process is often composed of a BARC etch step and a polysilicon main etch step, followed by a soft landing step (to preserve the gate oxide) and an overetch step. Each step is individually involved in the critical dimension (CD) control of the gate and contributes to some extent to the CD deviation. In theory, a very precise pattern transfer is possible for each step of the process if : 1) the etching is perfectly anisotropic, 2) the mask dimension is maintained intact during the process (no passivation layer deposition on the mask sidewall and no mask erosion). In practice, for each process step, etch products are deposited on the mask and on the feature sidewalls. The layer formed on the mask sidewalls generates a CD deviation whereas the passivation layer formed on the material being etched protects it against profile deformation. In this talk, a preliminary study of the CD deviation induced by each step of a polysilicon gate etch process is performed and correlated with sidewall analysis by X-ray photoelectron spectroscopy (XPS). Standard chemistries (HBr/Cl@sub2@/O@sub2@) and self clean chemistries (HBr/Cl@sub2@/O@sub2@/CF@sub4@) are compared. In final, for each process step, plasma operating conditions and chemistry are adjusted to minimize the CD deviation of the process and the most promising strategy is proposed.