Study of porous SiOCH patterning using metallic hard mask: challenges and solutions

Nicolas Posseme (1) , Thibaut David (1) , Thierry Chevolleau (2) , Maxime Darnon (2) , Fanny Bailly (3) , Régis Bouyssou (3) , Julien Ducote (3) , Hamed Chaabouni (2) , Mohamed El Kodadi (2) , Christophe Licitra (1) , Christophe Vérove (3) , Olivier Joubert (2)

1 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information
2 LTM - Laboratoire des technologies de la microélectronique
3 ST-CROLLES - STMicroelectronics [Crolles]

The choice of copper/low-k interconnect architectures is instrumental in achieving high device performances. Today, the implementation of porous low-k materials becomes mandatory in order to compensate metal resistance increase upon RC product. However, their introduction, which was initially planned for the 65nm technological node, was delayed to 45nm node due to integration issues. Using an integration strategy which combines porous SiOCH materials and metal hard masks, the difficulties and possible solutions are presented in this paper with emphasis on plasma etching.

Domaines: Physique [physics]

Nicolas Posseme, Thibaut David, Thierry Chevolleau, Maxime Darnon, Fanny Bailly, et al.. Study of porous SiOCH patterning using metallic hard mask: challenges and solutions. ECS Transactions, 2011, 35 (4), pp.667-685. ⟨10.1149/1.3572312⟩. ⟨hal-00629313⟩