3D IC Interconnect Parasitic Capacitance Extraction with a Reformulated PGD Algorithm - Laboratoire d'Electronique et Electromagnétisme Accéder directement au contenu
Article Dans Une Revue IEEE Transactions on Magnetics Année : 2017

3D IC Interconnect Parasitic Capacitance Extraction with a Reformulated PGD Algorithm

Résumé

Proper generalized decomposition (PGD) is a recently developed model order reduction (MOR) method based on the use of variable-separated representations. In this work, space variable-separated PGD is applied on 3D capacitance extraction of interconnects in integrated circuits (IC) to reduce its computational complexity. To make the PGD solver feasible, the complex boundary conditions are simplified by a characteristic function technique. 3D singular value decomposition (SVD) of the coefficient functions is avoided by using a reformulated PGD algorithm, and therefore the proposed method can effectively deal with problems with inhomogeneous dielectric layers and dummy fills. Numerical examples are given to verify the method.
Fichier non déposé

Dates et versions

hal-01513403 , version 1 (25-04-2017)

Identifiants

Citer

Yalan Li, Shuai Yan, Xiaoyu Xu, Pengfei Lyu, Zhuoxiang Ren. 3D IC Interconnect Parasitic Capacitance Extraction with a Reformulated PGD Algorithm. IEEE Transactions on Magnetics, 2017, 53 (6), pp.7200804. ⟨10.1109/TMAG.2017.2648852⟩. ⟨hal-01513403⟩
58 Consultations
0 Téléchargements

Altmetric

Partager

Gmail Facebook X LinkedIn More