Design Optimization of Through-Silicon Vias for Substrate-Integrated Waveguides embedded in High-Resistive Silicon Interposer

Matthias Wietstruck (1) , Steffen Marschmeyer (1) , Selin Tolunay Wipf (1) , Christian Wipf (1) , T. Voβ (1) , Matthieu Bertrand (2) , Emmanuel Pistono (3) , Giuseppe Acri (3) , Florence Podevin (3) , Philippe Ferrari (3) , Mehmet Kaynak (1)

1 IHP - Innovations for High Performance Microelectronics
2 L2E - Laboratoire d'Electronique et Electromagnétisme
3 RFIC-Lab - Laboratoire de Radio-Fréquence et d'Intégration de Circuits

In this work, the optimization of TSVs for SIWs embedded in a high-resistive silicon interposer is demonstrated. EM simulations are performed to analyze and optimize important TSV design parameters enabling silicon interposer technologies with low-loss SIWs working at mm-wave/THz frequencies. A silicon interposer using high resistive silicon and TSVs is fabricated and SIWs are characterized working from 110-170 GHz with very low attenuation of ~0.5 dB/mm.

Mots clés: through-silicon vias; silicon; substrates; dielectric loss; conductivity; metals; cutoff frequency

Domaines: Micro et nanotechnologies/Microélectronique

Matthias Wietstruck, Steffen Marschmeyer, Selin Tolunay Wipf, Christian Wipf, T. Voβ, et al.. Design Optimization of Through-Silicon Vias for Substrate-Integrated Waveguides embedded in High-Resistive Silicon Interposer. 20th Electronics Packaging Technology Conference (EPTC 2018), Dec 2018, Singapore, Singapore. ⟨hal-03158256⟩