High-level system modeling for rapid HW/SW architecture exploration

Chafic Jaber (1, 2, 3) , Andreas Kanstein , Ludovic Apvrille (2, 4) , Amer Baghdadi (5, 1) , Patricia Le Moënner , Renaud Pacalet (2, 4)

1 ELEC - Département Electronique
2 Télécom ParisTech
3 Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance
4 COMELEC - Département Communications & Electronique
5 Lab-STICC_TB_CACS_IAS

The increasing complexity of system-on-chip design especially the software part of those systems has stimulated much research work on design space exploration at the early stages of system development. In this paper we propose a new methodology for system modeling based on a specific UML profile. It defines a high design abstraction level for modeling and analyzing hardware resource sharing between system elements. Additionally, a SystemC-based simulator is developed in order to simulate modeled systems and evaluate their performance. Due to the high level of abstraction, the developed simulator enables fast exploration of design solutions. First promising results are presented and discussed over a mobile platform for the 3GPP LTE protocol stack.

Mots clés: Hardware/software co-design; Architecture exploration; UML; System modeling

Domaines: Electronique; Traitement du signal et de l'image [eess.SP]

Chafic Jaber, Andreas Kanstein, Ludovic Apvrille, Amer Baghdadi, Patricia Le Moënner, et al.. High-level system modeling for rapid HW/SW architecture exploration. IEEE/IFIP International Symposium on Rapid System Prototyping (RSP '09), Jun 2009, Paris, France. pp.88-94, ⟨10.1109/RSP.2009.27⟩. ⟨hal-02124754⟩