Spiking Neuron Hardware-Level Fault Modeling

Sarah A El-Sayed (1) , Theofilos Spyrou (1) , Antonios Pavlidis (1) , Engin Afacan (1) , Luis A Camuñas-Mesa (2) , Bernabé Linares-Barranco (2) , Haralampos-G. Stratigopoulos (1)

1 CIAN - Circuits Intégrés Numériques et Analogiques
2 IMSE-CNM - Instituto de Microelectrónica de Sevilla

The deployment of Artificial Intelligence (AI) hardware accelerators in a variety of applications, including safety-critical ones, requires assessing their inherent reliability to hardware-level faults and developing cost-effective fault tolerance techniques. This entails performing large-scale fault simulation experiments. However, transistor-level fault simulation is prohibitive and fault simulation should be carried out at a higher abstraction level. In this work, we focus on spiking neural networks (SNNs), and we follow a bottom-up approach starting from transistor-level simulations for developing a neuron behavioral-level fault model that can be readily employed for performing behavioral-level fault simulation of deep SNNs.

Domaines: Ingénierie assistée par ordinateur; Systèmes embarqués; Modélisation et simulation; Intelligence artificielle [cs.AI]; Micro et nanotechnologies/Microélectronique; Electronique

Sarah A El-Sayed, Theofilos Spyrou, Antonios Pavlidis, Engin Afacan, Luis A Camuñas-Mesa, et al.. Spiking Neuron Hardware-Level Fault Modeling. 26th IEEE International Symposium on On-Line Testing and Robust System Design, Jul 2020, Naples, Italy. ⟨10.1109/IOLTS50870.2020.9159745⟩. ⟨hal-02873418⟩