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FPGA reconfigurable architecture for MIMO V-BLAST detector

Hongzhi Wang 1 Pierre Leray 1 Jacques Palicot 1
1 IETR - Institut d'Electronique et de Télécommunications de Rennes
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https://hal-supelec.archives-ouvertes.fr/hal-00269227
Contributor : Myriam Andrieux <>
Submitted on : Wednesday, April 2, 2008 - 2:58:57 PM
Last modification on : Wednesday, April 8, 2020 - 3:29:12 PM

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  • HAL Id : hal-00269227, version 1

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CNRS | UNIV-RENNES1 | SUP_SCEE | SUPELEC | IETR_SCEE | IETR | UR1-UFR-ISTIC | SUP_IETR | UNIV-RENNES | INSA-GROUPE

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Hongzhi Wang, Pierre Leray, Jacques Palicot. FPGA reconfigurable architecture for MIMO V-BLAST detector. CODEST Telecommunications Workshop, Nov 2006, Xi'an, China. ⟨hal-00269227⟩

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