Architecture reconfigurable CBDRA basée sur l'opérateur CORDIC pour le traitement du signal: Application aux récepteurs MIMO

Abstract : "This article addresses the realization of reconfigurable architectures to answer the communication system requirement like high performance on data rate and flexibility supporting the evolution of future systems. We are particularly interested in MIMO applications. The proposed architectures use CORDIC (COordinate Rotation DIgital Computing) operator as common operator. Also the static and partial reconfiguration of FPGA is performed in view of an optimization and dynamic adaptation of hardware resources according to communication system specifications. The number of CORDIC operators can be changed by static reconfiguration to adapt to different MIMO receivers and different required data rate. The interconnections between CORDIC operators can be changed by partial and dynamic FPGA reconfiguration to optimize the hardware resources. The impact of step number of CORDIC operator on BER and MSE is also studied. Three MIMO receivers are realized in this architecture: V-BLAST Square Root, MMSE and CMA. The use of these architectures allows reducing the hardware resources without BER and MSE degradation."
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https://hal-supelec.archives-ouvertes.fr/hal-00441415
Contributor : Myriam Andrieux <>
Submitted on : Wednesday, December 16, 2009 - 8:53:48 AM
Last modification on : Friday, November 16, 2018 - 1:28:01 AM

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  • HAL Id : hal-00441415, version 1

Citation

Hongzhi Wang, Pierre Leray, Jacques Palicot. Architecture reconfigurable CBDRA basée sur l'opérateur CORDIC pour le traitement du signal: Application aux récepteurs MIMO. GRETSI 2009, Sep 2009, Dijon, France. 4 p. ⟨hal-00441415⟩

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