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Determination of the Behaviour of Self-Sampled Digital Phase-Locked Loops

Abstract : This paper deals with the stability of so-called “selfsampled” digital phase-locked-loops (PLLs). These systems are meant to be used as the nodes of autonomous clock distribution networks, where clock signals are locally generated in each node and each node is synchronized with its neighbours. Despite the absence of an absolute reference clock, it is possible to use the local irregular clock to trigger the operations of the digital loop filter. In this paper, we show that, in this mode of operation, PLLs can be modeled as autonomous piecewise-linear systems. We investigate what filter coefficients to choose in order to ensure stability and, hence synchronization. Two methods are explored, the first based on transient simulations, the second on linear matrix inequalities. It is shown that the second method yields much more conservative results than the first but that it cannot apply to all design options of self-sampled PLLs.
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Submitted on : Thursday, September 23, 2010 - 9:48:10 AM
Last modification on : Friday, January 8, 2021 - 5:32:07 PM
Long-term archiving on: : Friday, December 24, 2010 - 2:38:09 AM


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Jean-Michel Akre, Jérôme Juillard, Sorin Olaru, Dimitri Galayko, Eric Colinet. Determination of the Behaviour of Self-Sampled Digital Phase-Locked Loops. 53rd IEEE International Midwest Symposium on Circuits ans Systems (MWSCAS'10), Aug 2010, Seattle, United States. pp.1089-1092, ⟨10.1109/MWSCAS.2010.5548840⟩. ⟨hal-00520380⟩



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