A clock network of distributed ADPLLs using an asymmetric comparison strategy

A. Korniienko 1 Eric Colinet 2 Gérard Scorletti 3 E. Blanco 3 Dimitri Galayko 4 Jérôme Juillard 5
1 CEA-LETI - Laboratoire d'Electronique et des Technologies de l'Information
2 DSYS - Département Systèmes
3 Ampère
4 CIAN - Circuits Intégrés Numériques et Analogiques
LIP6 - Laboratoire d'Informatique de Paris 6
5 E3S - Supélec Sciences des Systèmes [Gif-sur-Yvette]
Abstract : in this paper, we describe an architecture of a distributed ADPLL (All Digitall Phase Lock Loop) network based on bang-bang phase detectors that are interconnected asymmetrically. It allows an automatic selection between two operating modes (uni- and bidirectional) to avoid mode-locking phenomenon, to accelerate the network convergence and to improve the robustness to possible network failures in comparison to simple unidirectional mode.
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Last modification on : Tuesday, May 14, 2019 - 11:03:37 AM
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A. Korniienko, Eric Colinet, Gérard Scorletti, E. Blanco, Dimitri Galayko, et al.. A clock network of distributed ADPLLs using an asymmetric comparison strategy. IEEE International Symposium on Circuit and Systems (ISCAS'10), May 2010, Paris, France. pp.3212-3215, ⟨10.1109/ISCAS.2010.5537932⟩. ⟨hal-00520988⟩

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