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ECOLE SUPÉRIEURE D'ÉLECTRICITÉ Une grande école d'ingénieurs au cœur des sciences de l'information,de l'énergie et des systèmes |
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Conference papers
A clock network of distributed ADPLLs using an asymmetric comparison strategy
Abstract : In this paper, we describe an architecture of a distributed ADPLL (All Digital Phase Lock Loop) network based on bang-bang phase detectors that are interconnected asymmetrically. It allows an automatic selection between two operating modes (uni- and bidirectional) to avoid mode-locking phenomenon, to accelerate the network convergence and to improve the robustness to possible network failures in comparison to simple unidirectional mode.
Cited literature [6 references]
https://hal-supelec.archives-ouvertes.fr/hal-00520988
Contributor : Karine El Rassi <>
Submitted on : Friday, September 24, 2010 - 4:39:32 PM
Last modification on : Wednesday, July 8, 2020 - 12:42:19 PM
Document(s) archivé(s) le : Saturday, December 25, 2010 - 2:41:13 AM
Contributor : Karine El Rassi <>
Submitted on : Friday, September 24, 2010 - 4:39:32 PM
Last modification on : Wednesday, July 8, 2020 - 12:42:19 PM
Document(s) archivé(s) le : Saturday, December 25, 2010 - 2:41:13 AM
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ISCAS_Kornienko.pdf
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