Novel loop architectures for enhancing linearity and resolution of analog-to-digital converters

Abstract : This paper proposes three mixed (analog and digital) loop architectures which involve an analog-to-digital converter and enhance its linearity and its resolution. Their benefits are discussed with mathematical models and high-level simulations (the ADC inserted in the loops is then a passive sigma-delta structure). One of the loop topologies is particularly highlighted: it is ideally able to enhance resolution by 5 bits without damaging bandwidth. The only added analog element is an active differential low-pass filter. The other operators are fully digital: a predictor and some models of the analog parts. The effect of some defaults, such as mismatch and common mode, is illustrated by high-level simulations. The needed accuracy for the digital parameters is evaluated to 16 bits. The test of a prototype realized in a 0.358m CMOS technology validates the principle and demonstrates that the critical element of the structure is the active differential filter.
Document type :
Journal articles
Complete list of metadatas

Cited literature [9 references]  Display  Hide  Download

https://hal-supelec.archives-ouvertes.fr/hal-00542287
Contributor : Karine El Rassi <>
Submitted on : Thursday, December 2, 2010 - 11:12:19 AM
Last modification on : Thursday, March 29, 2018 - 11:06:05 AM
Long-term archiving on : Thursday, March 3, 2011 - 2:46:31 AM

File

SG_Novel_loop.pdf
Files produced by the author(s)

Identifiers

Collections

Citation

Sylvie Guessab, Philippe Benabes. Novel loop architectures for enhancing linearity and resolution of analog-to-digital converters. Analog Integrated Circuits and Signal Processing, Springer Verlag, 2010, 65 (3), pp.359-377. ⟨10.1007/s10470-009-9400-0⟩. ⟨hal-00542287⟩

Share

Metrics

Record views

226

Files downloads

187