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Design and VHDL Modeling of All-Digital PLLs

Abstract : In this paper, a VHDL model of a second-order alldigital phase-locked loop (ADPLL) based on bang-bang phase detectors is presented. The developed ADPLL is destined to be a part of a distributed clock generators based on networks of the ADPLL. The paper presents an original model and architecture of a digital multi-bit phase-frequency detector (PFD), and describes in details the VHDL modeling of metastability issues related with asynchronous operation of the digital PFD. This particular architecture of the digital PHD is required by the synchronised operation of the ADPLL network in the context of distributed clock generator. The whole ADPLL model have been validated by purely behavioral (VHDL) and mixed simulation, in which the digital PFD detector was represented by its transistorlevel model.
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Submitted on : Tuesday, January 4, 2011 - 4:30:01 PM
Last modification on : Friday, January 8, 2021 - 5:32:07 PM
Long-term archiving on: : Tuesday, April 5, 2011 - 3:04:00 AM


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Eldar Zianbetov, Mohammad Javidan, François Anceau, Dimitri Galayko, Eric Colinet, et al.. Design and VHDL Modeling of All-Digital PLLs. 8th IEEE International NEWCAS Conference (NEWCAS'10), Jun 2010, Montreal, Canada. pp.293-296, ⟨10.1109/NEWCAS.2010.5603947⟩. ⟨hal-00551825⟩



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