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Implementation Scenario for Teaching Partial Reconfiguration of FPGA

Pierre Leray 1 Amor Nafkha 1 Christophe Moy 1
1 IETR - Institut d'Electronique et de Télécommunications de Rennes
Abstract : We present in this paper a lab on partial reconfiguration (PR) of FPGA for a video application. This lab is dedicated to last year engineering students. The implementation target is a Xilinx Virtex5 of a ML506 design kit board. The structure of the proposed design, as well as the designing steps and the obtained results are detailled. This lab is based on the research done by the authors in the domain of software radio and cognitive radio during last decade.
Keywords : education ICAP Virtex partial reconfiguration of FPGA
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Conference papers
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https://hal-supelec.archives-ouvertes.fr/hal-00606401
Contributor : Myriam Andrieux <>
Submitted on : Wednesday, July 6, 2011 - 1:38:19 PM
Last modification on : Friday, January 8, 2021 - 3:42:42 AM

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  • HAL Id : hal-00606401, version 1

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CNRS | UNIV-RENNES1 | SUPELEC | SUP_SCEE | IETR | IETR_SCEE | UR1-UFR-ISTIC | SUP_IETR | UNIV-RENNES | INSA-GROUPE | INSA-RENNES

Citation

Pierre Leray, Amor Nafkha, Christophe Moy. Implementation Scenario for Teaching Partial Reconfiguration of FPGA. 6th International Workshop on Reconfigurable Communication Centric Systems-on-Chip (ReCoSoC), Jun 2011, Montpellier, France. ⟨hal-00606401⟩

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