A 2GHz CMOS DCO with optimized architecture for high speed clocking

Eldar Zianbetov; Mohammad Javidan; François Anceau; Dimitri Galayko; Eric Colinet; Jérôme Juillard

A 2GHz CMOS DCO with optimized architecture for high speed clocking

Eldar Zianbetov ¹ Mohammad Javidan ¹ François Anceau ¹ Dimitri Galayko ¹ Eric Colinet ² Jérôme Juillard ³

1 CIAN - Circuits Intégrés Numériques et Analogiques

LIP6 - Laboratoire d'Informatique de Paris 6

2 CEA-LETI - Laboratoire d'Electronique et des Technologies de l'Information

3 E3S - Supélec Sciences des Systèmes [Gif-sur-Yvette]

Document type :

Conference papers

Domain :

Engineering Sciences [physics] / Electronics

Engineering Sciences [physics] / Signal and Image processing

Computer Science [cs] / Signal and Image Processing

Complete list of metadatas

https://hal-supelec.archives-ouvertes.fr/hal-00631096
Contributor : Karine El Rassi <>
Submitted on : Tuesday, October 11, 2011 - 2:44:49 PM
Last modification on : Wednesday, May 15, 2019 - 3:39:15 AM

A 2GHz CMOS DCO with optimized architecture for high speed clocking

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A 2GHz CMOS DCO with optimized architecture for high speed clocking

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