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A 2GHz CMOS DCO with optimized architecture for high speed clocking

Eldar Zianbetov 1 Mohammad Javidan 1 François Anceau 1 Dimitri Galayko 1 Eric Colinet 2 Jérôme Juillard 3
1 CIAN - Circuits Intégrés Numériques et Analogiques
LIP6 - Laboratoire d'Informatique de Paris 6
2 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information
3 E3S - Supélec Sciences des Systèmes
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Conference papers
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https://hal-supelec.archives-ouvertes.fr/hal-00631096
Contributor : Karine El Rassi <>
Submitted on : Tuesday, October 11, 2011 - 2:44:49 PM
Last modification on : Friday, January 8, 2021 - 5:32:07 PM

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  • HAL Id : hal-00631096, version 1

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CEA | CNRS | SUPELEC | UPMC | LIP6 | DRT | LIP6-CIAN | LETI | SORBONNE-UNIVERSITE | CEA-GRE | SU-SCIENCES

Citation

Eldar Zianbetov, Mohammad Javidan, François Anceau, Dimitri Galayko, Eric Colinet, et al.. A 2GHz CMOS DCO with optimized architecture for high speed clocking. International Symposium on Circuits and Systems (ISCAS'11), May 2011, Rio de Janeiro, Brazil. pp.2845-2848. ⟨hal-00631096⟩

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