A Software Defined Radio Structure for 2nd and 3rd Genaration Mobile Communications Standards, IEEE 6th Int. Symp. On Spread-Spectrum Tech. and Appli, 2000. ,
Fast digital convolution using Fermat transforms, Southwest IEEE Conf. Rec, pp.538-543, 1973. ,
On the complexity of decoding Reed-Solomon codes (Corresp.), IT-22, pp.237-238, 1976. ,
DOI : 10.1109/TIT.1976.1055516
Fast Convolution using fermat number transforms with applications to digital filtering, IEEE Transactions on Acoustics, Speech, and Signal Processing, vol.22, issue.2, 1974. ,
DOI : 10.1109/TASSP.1974.1162555
The fast decoding of Reed-Solomon codes using Fermat transforms (Corresp.), IEEE Transactions on Information Theory, vol.24, issue.4, p.24, 1978. ,
DOI : 10.1109/TIT.1978.1055902
A Reconfigurable Architecture for the FFT Operator in a Software Radio Context, IEEE ISCAS, 2006. ,
A Reconfigurable Butterfly Architecture for Fourier and Fermat Transforms, IEEE WSR, 2006. ,
URL : https://hal.archives-ouvertes.fr/hal-00083992
Complexity Evaluation of a Re-Configurable Butterfly with FPGA for Software Radio Systems, 2007 IEEE 18th International Symposium on Personal, Indoor and Mobile Radio Communications, 2007. ,
DOI : 10.1109/PIMRC.2007.4394479
URL : https://hal.archives-ouvertes.fr/hal-00186224
FPGA implementation of a reconfigurable FFT for multi-standard systems in software radio context, IEEE Transactions on Consumer Electronics, vol.55, issue.2, 2009. ,
On the FPGA Implementation of the Fourier Transform over Finite Fields GF (2 m ), IEEE ISCIT, 2007. ,
A Suggestion for a Fast Multiplier, IEEE Transactions on Electronic Computers, vol.13, issue.1, pp.14-17, 1964. ,
DOI : 10.1109/PGEC.1964.263830
Some Schemes for Parallel Multipliers, Alta Frequenza, vol.34, pp.349-356, 1965. ,
Vlsi designs for multiplication over finite fields GF(2m), Proc. Sixth Int. Conf. Applied Algebra, Algebraic Algorithms , and Error-Correcting Codes (AAECC-6), pp.297-309, 1988. ,
DOI : 10.1007/3-540-51083-4_67
Systolic Multipliers For Finite Fields GF(2m), IEEE Transactions on Computers, pp.33-357, 1984. ,
Custom VLSI Design of Efficient Low Latency and Low Power Finite Field Multiplier for Reed-Solomon Codec, IEEE International Symposium on Circuits and Systems ISCAS'01, pp.574-577, 2001. ,
VLSI Architecture For Non- Sequential Inversion Over GF (2 m ) Using the Euclidean Algorithm, Int. Conf. On Signal Processing Applications and Technology, 1997. ,
A combined 16-bit binary and dual Galois field multiplier, IEEE Workshop on Signal Processing Systems, pp.63-68, 2002. ,
DOI : 10.1109/SIPS.2002.1049686
Yu and Shanzhen Xing Fixed-Point Multiplier Evaluation and Design with FPGA, Proceedings of SPIE, vol.3844, 1999. ,