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Leakage Power Consumption In FPGAs: Thermal Analysis

Abstract : Current power saving techniques have been focused on reducing the dynamic power consumption induced by switching activity in CMOS digital circuits. Among these techniques, we can cite the clock gating, dynamic voltage frequency scaling, adaptive voltage scaling, and multiple voltage thresholds. Recently, as transistors sizes decrease, the leakage power consumption has become a non-negligible and dominating part of the total power consumption. Thus, it is essential to take care of this new constraint in order to design low-power embedded wireless communication systems. It's well known that there is a strong relationship between leakage power and dietemperature so that the largest leakage power consumption is associated with the largest temperature. In this paper we give a detailed analysis of FPGA leakage power consumption based on die temperature measurements. Also, after slicing the FPGA area into several rectangular regions, we investigate whether dynamic partial reconfiguration technique can be performed over different regions to decrease average die-temperature, and consequently the leakage power consumption.
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Contributor : Anne Cloirec <>
Submitted on : Tuesday, September 18, 2012 - 2:09:16 PM
Last modification on : Monday, October 5, 2020 - 9:50:17 AM


  • HAL Id : hal-00733326, version 1


Amor Nafkha, Jacques Palicot, Pierre Leray, Yves Louët. Leakage Power Consumption In FPGAs: Thermal Analysis. IEEE ISWCS 2012, Aug 2012, Paris, France. 5 p. ⟨hal-00733326⟩



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