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Design Strategy for Clocking and Runtime Parametrization in the Channelization Accelerator of Multistandard Radios

Abstract : The channelization function in the digital front-end is one of the most computationally intensive kernels in the software defined radio baseband. The channelization tasks of filtering and decimation can be efficiently performed by a multistage decimation filter structure. The individual filter stages within the decimation filter may operate at different clock rates which may be incommensurate. The multiplicity of clock signals required to support multiple standards necessitates that the clock generation circuitry be parameterizable. In addition to the clock rates of the filter stages, some of the filter stages themselves may need to be fully or partially parameterizable. The current work has two major contributions. Firstly we propose an architecture for generating the multiplicity of clock signals required in a each mode of a multistandard channelization accelerator using a single reference clock. Secondly we propose a mechanism for loading and locally storing the configuration data for the clock generation circuitry as well as the accelerator datapath while switching between standards.
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https://hal-supelec.archives-ouvertes.fr/hal-00868259
Contributor : Myriam Andrieux <>
Submitted on : Tuesday, October 1, 2013 - 11:21:13 AM
Last modification on : Wednesday, October 14, 2020 - 3:53:38 AM

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Michael Navin, A. P. Vinod, Christophe Moy, Jacques Palicot. Design Strategy for Clocking and Runtime Parametrization in the Channelization Accelerator of Multistandard Radios. Journal of Signal Processing Systems, Springer, 2015, 78 (2), pp.171-177. ⟨10.1007/s11265-013-0849-9⟩. ⟨hal-00868259⟩

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