A 1.62GS/s Time-Interleaved SAR ADC with fully digital background mismatch calibration achieving interleaving spurs below 70dBFS

Abstract : Today's applications such as broadband satellite receivers, cable TVs, and software-defined radios require highly efficient ADCs with high sampling rates and high resolutions. A time-interleaved ADC (TIADC) is a popular architecture used to achieve this goal. However, this structure suffers from mismatches between the sub-converters, which cause errors on the output signal, and more significantly, decrease the SFDR. These mismatches can be a severe limitation in applications such as satellite reception, where both narrowband and wideband signals are used. This paper introduces digital derivative-based estimation of timing mismatches. Gain, offset and skew mismatch calibrations are performed entirely in the digital domain through equalization.
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ISSCC 2014, Feb 2014, San Franscisco, United States. Proceedings of the 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp.386-388, 2014, 〈10.1109/ISSCC.2014.6757481〉
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Nicolas Le Dortz, J.-P. Blanc, Thierry Simon, Sarah Verhaeren, E. Rouat, et al.. A 1.62GS/s Time-Interleaved SAR ADC with fully digital background mismatch calibration achieving interleaving spurs below 70dBFS. ISSCC 2014, Feb 2014, San Franscisco, United States. Proceedings of the 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp.386-388, 2014, 〈10.1109/ISSCC.2014.6757481〉. 〈hal-01075055〉

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