Control induced explicit time-scale separation to attain DC voltage stability for a VSC-HVDC terminal

Abstract : This paper presents a new control scheme to regulate the DC voltage of a VSC terminal. It significantly simplifies the control design process itself and in general also results in an uncomplicated and efficient control architecture. Firstly, an equivalent state space model established in a synchronous $dq$ reference frame is presented. Next we split the overall system into two interconnected subsystems and suppose that different dynamics can be imposed on them under their own sub-controllers. During the design process, we use a reduced model obtained by singular perturbation techniques instead of the original system. The developed control law is actually based on this reduced model and an explicit division of time scales. Simulation results clearly demonstrate that the controller based on the reduced model can regulate the DC voltage with good performances and in the meantime, the real DC voltage can be well approximated by its reduced model.
Domain :

https://hal-supelec.archives-ouvertes.fr/hal-01102679
Contributor : Myriam Baverel <>
Submitted on : Tuesday, January 13, 2015 - 12:26:31 PM
Last modification on : Wednesday, April 8, 2020 - 4:01:53 PM

Citation

Y. Chen, Gilney Damm, A. Benchaib, Mariana Netto, Françoise Lamnabhi-Lagarrigue. Control induced explicit time-scale separation to attain DC voltage stability for a VSC-HVDC terminal. 19th IFAC World Congress on International Federation of Automatic Control (IFAC 2014), Aug 2014, CapeTown, South Africa. pp.540-545, ⟨10.3182/20140824-6-ZA-1003.01298⟩. ⟨hal-01102679⟩

Record views