High-resolution detection of Au catalyst atoms in Si nanowires, Nature Nanotechnology, vol.85, issue.3, pp.168-173, 2008. ,
DOI : 10.1038/nnano.2008.5
Growth of vertically aligned Si wire arrays over large areas (>1cm2) with Au and Cu catalysts, Growth of vertically aligned Si wire arrays over large areas (> 1 cm) with Au and Cu catalysts, p.103110, 2007. ,
DOI : 10.1063/1.2779236
Enhanced absorption and carrier collection in Si wire arrays for photovoltaic applications, Nature Materials, vol.9, issue.3, pp.239-244, 2010. ,
Thermal analysis and modeling of embedded processors, Computers & Electrical Engineering, vol.36, issue.1, pp.142-154, 2010. ,
DOI : 10.1016/j.compeleceng.2009.07.001
Three-dimensional 35 nF/mm/sup 2/ MIM capacitors integrated in BiCMOS technology, Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005., p.121, 2005. ,
DOI : 10.1109/ESSDER.2005.1546600
Modeling and optimization of series resistance of planar MIM capacitors, Solid State Elec, pp.50-1244, 2006. ,
Impact of TiN Plasma Post-Treatment on Alumina Electron Trapping, IEEE Transactions on Device and Materials Reliability, vol.7, issue.2, pp.242-251, 2007. ,
DOI : 10.1109/TDMR.2007.901084
Nanotubular metal???insulator???metal capacitor arrays for energy storage, Nature Nanotechnology, vol.25, issue.5, pp.292-296, 2009. ,
DOI : 10.1038/nnano.2009.37
Si nanowire growth and characterization using a microelectronics-compatible catalyst: PtSi, Applied Physics Letters, vol.89, issue.23, pp.89-233111, 2006. ,
DOI : 10.1063/1.2402118
URL : https://hal.archives-ouvertes.fr/hal-00394743
GeOI and SOI 3D Monolithic Cell integrations for High Density Applications, Dig. Of tech, 2009. ,
Etude des non-linéarités de permittivité de diélectriques utilisés en microélectronique Application aux capacités MIM, Thèse de l'Université d'Aix-Marseille I, Bernardini, Modélisation des structures Metal-Oxyde-Semiconducteur, 2006. ,
Donor deactivation in silicon nanostructures, Nature Nanotechnology, vol.41, issue.2, pp.103-107, 2009. ,
DOI : 10.1038/nnano.2008.400
High-Capacity, Self-Assembled Metal???Oxide???Semiconductor Decoupling Capacitors, IEEE Electron Device Letters, vol.25, issue.9, pp.25-622, 2004. ,
DOI : 10.1109/LED.2004.834637
Ultra-dense silicon nanowires: A technology, transport and interfaces challenges insight, Microelec, Appl. Phys. Lett, pp.1198-1202, 2000. ,
Controlled p- and n-type doping of Fe2O3 nanobelt field effect transistors, Applied Physics Letters, vol.87, issue.1, p.13113, 2005. ,
DOI : 10.1063/1.1977203
Vertically Stacked SiGe Nanowire Array Channel CMOS Transistors, IEEE Electron Device Letters, vol.28, pp.3-211, 2007. ,
Integration of high-performance RF passive modules (MIM capacitors and inductors) in advanced BEOL, Microelectronic Engineering, vol.85, issue.10, p.85, 2008. ,
DOI : 10.1016/j.mee.2008.03.017
Phase-change-memory-based storage elements for configurable logic, 2010 International Conference on Field-Programmable Technology, 2010. ,
DOI : 10.1109/FPT.2010.5681535
Can We Go Towards True 3-D Architectures?, WACI session, 48th Design Automation Conference (DAC), 2011. ,
Dopant profiling and surface analysis of silicon nanowires using capacitance???voltage measurements, Nature Nanotechnology, vol.13, issue.5, pp.311-314, 2009. ,
DOI : 10.1038/nnano.2009.43
CMOS compatible strategy based on selective atomic layer deposition of a hard mask for transferring block copolymer lithography patterns, Nanotechnology, vol.21, issue.43, pp.43-435301, 2010. ,
DOI : 10.1088/0957-4484/21/43/435301
URL : https://hal.archives-ouvertes.fr/hal-00944905
Evolution of materials technology for stacked-capacitors in 65 nm embedded-DRAM, Solid-State Electronics 49, pp.1767-1775, 2005. ,
Silicon Vertically Integrated Nanowire Field Effect Transistors, Nano Letters, vol.6, issue.5, pp.973-977, 2006. ,
DOI : 10.1021/nl060166j
Epitaxial growth of silicon nanowires using an aluminium catalyst, Nature Nanotechnology, vol.10, issue.3, pp.186-189, 2006. ,
DOI : 10.1038/nnano.2006.133
Characteristics of vapor???liquid???solid grown silicon nanowire solar cells, Solar Energy Materials and Solar Cells, vol.93, issue.8, pp.1388-1393, 2009. ,
DOI : 10.1016/j.solmat.2009.02.024
Nanowires, The Journal of Physical Chemistry C, vol.113, issue.19, pp.8143-8146, 2009. ,
DOI : 10.1021/jp901630f
Room-temperature oxidation of silicon catalysed by, Appl. Phys. Lett, pp.56-2519, 1990. ,
Ultrahigh Capacitance Density for Multiple ALD-Grown MIM Capacitor Stacks in 3-D Silicon, MIM in 3D: Dream or reality?, Microelectronic Engineering 88, pp.740-742, 2008. ,
DOI : 10.1109/LED.2008.923205
Electrical conduction and dielectric breakdown in aluminium oxide insulator on silicon, Silicon Porosification : State of the Art, pp.121-153, 2000. ,
Confined VLS growth and structural characterization of silicon nanoribbons, Microelectronic Engineering, vol.87, issue.5-8, pp.1522-1526, 2010. ,
DOI : 10.1016/j.mee.2009.11.053
URL : https://hal.archives-ouvertes.fr/hal-00549560
Alternative catalysts for VSS growth of silicon and germanium nanowires, Journal of Materials Chemistry, vol.411, issue.7, pp.849-857, 2009. ,
DOI : 10.1002/adma.200800440
Light emission microscopy for reliability studies, Microelectronic Engineering, vol.49, issue.1-2, pp.169-180, 1999. ,
DOI : 10.1016/S0167-9317(99)00437-2
Automatic statistical full quantum analysis of C-V and I-V characteristics for advanced MOS gate stacks, Microelectronic Engineering, vol.84, issue.9-10, pp.2408-2411, 2007. ,
DOI : 10.1016/j.mee.2007.04.026
URL : https://hal.archives-ouvertes.fr/hal-00393151
Growth characteristics of silicon nanowires synthesized by vaporliquid-solid growth in nanoporous alumina templates, Europ. Photo. Sol. E. Conf. J. of Crystal Growth, vol.254, pp.14-22, 2003. ,
Metal-assisted chemical etching in HF/H 2 O 2 produces porous silicon, Appl. Phys. Lett, pp.77-2572, 2000. ,
Multifunctional CuO nanowire devices: p-type field effect transistors and CO gas sensors, Nanotechnology, vol.20, issue.8, p.85203, 2009. ,
DOI : 10.1088/0957-4484/20/8/085203
A Laser Ablation Method for the Synthesis of Crystalline Semiconductor Nanowires, Science, vol.279, issue.5348, pp.208-211, 1998. ,
DOI : 10.1126/science.279.5348.208
Nanowire Nanosensors for Highly Sensitive and Selective Detection of Biological and Chemical Species, Science, vol.293, issue.5533, pp.1289-1292, 2001. ,
DOI : 10.1126/science.1062711
Nanowire Crossbar Arrays as Address Decoders for Integrated Nanosystems, Science, vol.302, issue.5649, pp.1377-1379, 2003. ,
DOI : 10.1126/science.1090899
Coaxial silicon nanowires as solar cells and nanoelectronic power sources, Coaxial silicon nanowires as solar cells and nanoelectronic power sources, pp.885-889, 2007. ,
DOI : 10.1038/nature06181
Nanowire and Its Field Emission Property, Lissorgues, P. Bildstein, Filtres à capacités commutées, pp.2429-2431, 2005. ,
DOI : 10.1021/cm800079c
Demystifying Switched Capacitor Circuits, Chapitre 6 : Switched-Capacitor DC-DC Converters, pp.223-245, 2006. ,
In situ Control of Atomic-Scale Si Layer with Huge Strain in the Nanoheterostructure NiSi/Si/NiSi through Point Contact Reaction, Nano Letters, vol.7, issue.8, pp.2389-2394, 2007. ,
DOI : 10.1021/nl071046u
Scalable Approach for Vertical Device Integration of Epitaxial Nanowires, Nano Letters, vol.9, issue.5, pp.5-1830, 2009. ,
DOI : 10.1021/nl803776a
Fabrication of individually seeded nanowire arrays by vapour???liquid???solid growth, Nanotechnology, vol.14, issue.12, 2003. ,
DOI : 10.1088/0957-4484/14/12/004
On-chipe digital power supply control for systemon-chip applications, Proc. IEEE ISLPED'05, pp.311-315, 2005. ,
Influence of N2/H2 plasma treatment on chemical vapor deposited TiN multilayer structures for advanced CMOS technologies, Materials Science and Engineering: B, vol.102, issue.1-3, p.358, 2003. ,
DOI : 10.1016/S0921-5107(02)00619-0
Wafer-scale patterning of sub-40 nm diameter and high aspect ratio (>50:1) silicon pillar arrays by nanoimprint and etching, Nanotechnology, vol.19, issue.34, p.345306, 2008. ,
DOI : 10.1088/0957-4484/19/34/345301
Initial stages of electrodeposition of metal nanowires in nanporous templates, Electrochem. Act, pp.53-205, 2007. ,
Palladium catalyzed formation of carbon nanofibers by plasma enhanced chemical vapor deposition, Carbon, vol.45, issue.2, pp.424-428, 2007. ,
DOI : 10.1016/j.carbon.2006.08.019
Vertically Stacked Silicon Nanowire Transistors Fabricated by Inductive Plasma Etching and Stress-Limited Oxidation, IEEE Electron Device Letters, vol.30, issue.5, pp.5-520, 2009. ,
DOI : 10.1109/LED.2009.2014975
Synthesis of branched 'nanotrees' by controlled seeding of multiple branching events, Nature Materials, vol.3, issue.6, pp.380-384, 2004. ,
Silicon Nanowires: A Review on Aspects of their Growth and their Electrical Properties, Advanced Materials, vol.420, issue.3, p.2681, 2009. ,
DOI : 10.1002/adma.200803754
Diameter-Dependent Growth Direction of Epitaxial Silicon Nanowires, Nano Letters, vol.5, issue.5, pp.931-935, 2005. ,
DOI : 10.1021/nl050462g
Realization of a Silicon Nanowire Vertical Surround-Gate Field-Effect Transistor, Silicon Nanowires: A review on Aspects of their Growth and their Electrical Properties, pp.85-88, 2006. ,
DOI : 10.1002/smll.200500181
Synthesis and Properties of Single-Crystal FeSi Nanowires, Nano Letters, vol.6, issue.8, pp.1617-1621, 2006. ,
DOI : 10.1021/nl060550g
Metallic Single-Crystal CoSi Nanowires via Chemical Vapor Deposition of Single-Source Precursor, The Journal of Physical Chemistry B, vol.110, issue.37, pp.18142-18146, 2006. ,
DOI : 10.1021/jp064646a
Silicon nanowhiskers grown on ???111???Si substrates by molecular-beam epitaxy, Applied Physics Letters, vol.84, issue.24, p.4968, 2004. ,
DOI : 10.1063/1.1762701
Magnetic Properties of Single-Crystalline CoSi Nanowires, Nano Letters, vol.7, issue.5, pp.1240-1245, 2007. ,
DOI : 10.1021/nl070113h
Nanowires, The Journal of Physical Chemistry C, vol.111, issue.26, pp.9072-9076, 2000. ,
DOI : 10.1021/jp071707b
URL : https://hal.archives-ouvertes.fr/hal-00112196
A Silicon Interposer With an Integrated SrTiO 3 Thin Film Decoupling Capacitor and Through-Silicon Vias, Trans. On Comp, 2010. ,
Silicon nanowire oxidation: the influence of sidewall structure and gold distribution, Nanotechnology, vol.20, issue.40, p.405607, 2009. ,
DOI : 10.1088/0957-4484/20/40/405607
Realization of Vertical and Zigzag Single Crystalline Silicon Nanowire Architectures, J. Phys. Chem. C Appl. Phys. Lett, vol.114, issue.7, pp.3798-3803, 2007. ,
Single-Crystal Semiconducting Chromium Disilicide Nanowires Synthesized via Chemical Vapor Transport, Chemistry of Materials, vol.19, issue.13, p.3238, 2007. ,
DOI : 10.1021/cm0707307
Selective formation of silicon nanowires on pre-patterned substrates, Applied Surface Science, vol.255, issue.6, pp.3752-3758, 2009. ,
DOI : 10.1016/j.apsusc.2008.10.025
Epitaxial growth of silicon nanowires using an aluminium catalyst, Nature Nanotechnology, vol.10, issue.3, pp.186-189, 2006. ,
DOI : 10.1038/nnano.2006.133
Arrayed Si???SiGe Nanowire and Heterostructure Formations via Au-Assisted Wet Chemical Etching Method, Silicon-Nanowire Transistors with Intruded Nickel-Silicide Contacts, pp.37-40, 2006. ,
DOI : 10.1149/1.3093036
Faceted sidewalls of silicon nanowires: Au-induced structural reconstructions and electronic properties, Physical Review B, vol.81, issue.11, p.115403, 2010. ,
DOI : 10.1103/PhysRevB.81.115403
URL : https://hal.archives-ouvertes.fr/hal-00549070
Semiconductor Nanowire: What???s Next?, Nano Letters, vol.10, issue.5, pp.1529-1536, 2010. ,
DOI : 10.1021/nl100665r
Structures and energetics of hydrogen-terminated silicon nanowire surfaces, The Journal of Chemical Physics, vol.123, issue.14, p.144703, 2005. ,
DOI : 10.1063/1.2047555
Nanowire Crossbar Arrays as Address Decoders for Integrated Nanosystems, Science, vol.302, issue.5649, pp.1377-1379, 2003. ,
DOI : 10.1126/science.1090899
Nanonets, Angewandte Chemie International Edition, vol.57, issue.40, pp.7681-7684, 2008. ,
DOI : 10.1002/anie.200802744
Ordered Arrays of <100>-Oriented Silicon Nanorods by CMOS- Compatible Block Copolymer Lithography, Nano Lett, vol.7, issue.6, pp.1516-1520, 2007. ,
Silicon nanowire integration in a SiO2 template made by conventional lithography and etching process, GDR Nanofils, 2009. ,
Study and comparison of silicon nanostructures for MOS devices : CVD vs Epitaxy, MRS Fall Meeting, 2010. ,
Can we go towards true 3-D architectures?, Proceedings of the 48th Design Automation Conference on, DAC '11, pp.5-10 ,
DOI : 10.1145/2024724.2024790
Study of CVD nanowire high-k metal interface quality for interconnect level MOS devices, Microelectronic Engineering, vol.88, pp.1228-1233, 2011. ,
URL : https://hal.archives-ouvertes.fr/hal-00641302
Dispositif microélectronique à niveaux métalliques d'interconnexion connectés par des vias programmables ,