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H. Jeong, K. Song, I. H. Park, T. Kim, and Y. S. Lee, ?A new capacitorless 1T DRAM cell: Surrounding gate MOSFET with vertical channel (SGVC cell)A new capacitorless 1T DRAM cell: Surrounding gate MOSFET with vertical channel (SGVC cell)?, Nanotechnology, IEEE Transactions on. ?ol. ?, issue.3, pp.3-5, 2007.

H. K. Chung, H. Jeong, Y. S. Lee, J. Y. Song, and J. P. Kim, A capacitor-less 1T-DRAM cell with vertical surrounding gates using gate-induced drain-leakage (GIDL) current, 2008 IEEE Silicon Nanoelectronics Workshop, pp.1-2, 2008.
DOI : 10.1109/SNW.2008.5418470

N. Rodriguez, F. Gamiz, and S. Cristoloveanu, ?A-RAM memory cell: concept and operation?, Electron Device Letters, pp.972-974, 2010.

N. Rodriguez, C. Navarro, F. Gamize, F. Andrieu, and O. Faynot, ?Experimental demonstration of capacitorless A2RAM cells on silicon-on-insulator? Electron Device Letters, pp.1717-1719, 2012.

M. G. Ertosun, P. Kapur, and K. C. Saraswat, ?A highly scalable capacitorless double gate quantum well single transistor DRAM: 1T-QW DRAM?, Electron Device Letters, IEEE, vol.29, issue.12, pp.140-1407, 2008.

M. H. Cho, C. Shin, and T. J. Liu, ?Convex channel design for improved capacitorless DRAM retention time?, Simulation of semiconductor processes and devices, International Conference on, pp.1-4, 2009.

T. Poren, H. Ru, and ?. , Dake, ?Performance improvement of capacitorless dynamic random access memory cell with band-gap engineered source and drain?, Jpn. J. Appl. Phys, vol.49, 2010.

Y. Choi, J. Han, S. Kim, D. Kim, and M. Jang, ?High speed flash memory and 1T-DRAM on dopant segregated Schottky barrier (DSSB) FinFET SONOS device for multi-functional SoC applications?, Electron Device Meeting, IEEE International, pp.1-4, 2008.

S. Eminente, S. Cristoloveanu, R. Clerc, A. Ohata, and G. Ghibaudo, Ultra-thin fully-depleted SOI MOSFETs: Special charge properties and coupling effects, Solid-State Electronics, vol.51, issue.2, pp.239-244, 2007.
DOI : 10.1016/j.sse.2007.01.016
URL : https://hal.archives-ouvertes.fr/hal-00146784

K. Park, M. Bawedin, J. Lee, Y. Bae, and K. Na, Fully depleted double-gate MSDRAM cell with additional nonvolatile functionality, Solid-State Electronics, vol.67, issue.1, pp.17-22, 2012.
DOI : 10.1016/j.sse.2011.07.013

K. Park, C. M. Park, S. H. Kong, and J. Lee, Novel Double-Gate 1T-DRAM Cell Using Nonvolatile Memory Functionality for High-Performance and Highly Scalable Embedded DRAMs, IEEE Transactions on Electron Devices, vol.57, issue.3, pp.614-619, 2010.
DOI : 10.1109/TED.2009.2038650

J. Han, S. Choi, D. Kim, D. Moon, and Y. Choi, ?Gate-to-source/drain nonoverlap device for soft-program immune unified RAM (URAM)?, Electron Device Letters, pp.44-546, 2009.

S. Choi, C. Kim, S. Kim, and Y. Choi, ?Improvement of the sensing window on a capacitorless 1T- DRAM of a finFET-based unified RAM?, Electron Devices, IEEE Transactions on S. Cristoloveanu. ?Hysteresis Effects in FinFETs with ONO Buried Insulator? ECS Transaction, vol.??, issue.12, pp.3228-3231, 2009.

S. Chang, M. Bawedin, W. Xiong, S. C. Jeon, J. Lee et al., A FinFET memory with remote carrier trapping in ONO buried insulator, Microelectronic Engineering, vol.88, issue.7, pp.1203-1206, 2011.
DOI : 10.1016/j.mee.2011.03.034

S. Chang, M. Bawedin, W. Xiong, J. Lee, J. Lee et al., ?FinFlash with buried storage ONO layer for flash memory application?, Solid-State Electronics, pp.59-66, 2012.

S. Chang, M. Bawedin, W. Xiong, J. Lee, J. Lee et al., ?Remote carrier trapping in FinFETs with ONO buried layer: Temperature effects?, Microelectronics Reliability, pp.38-393, 2013.

S. Chang, M. Cheralathan, M. Bawedin, B. Iniguez, B. Bayraktaroglu et al., Sorin Cristoloveanu, ?Mobility Behavior and Models for Fully Depleted Nanocrystalline ZnO Thin Film Transistors? will be published in Solid-State Electronics

S. Chang, M. Bawedin, W. Xiong, J. Lee, J. Lee et al., Multi-Bit Unified Memory Concept in FinFETs with ONO Buried Insulator, ECS Transactions, vol.54, issue.1, pp.321-328, 2013.
DOI : 10.1149/05401.0321ecst

. Cristoloveanu, ?Investigation of Hysteresis Memory Effects in SOI FinFETs with ONO Buried Insulator?, IEEE SOI Conference, 2010.

S. Chang, M. Bawedin, W. Xiong, J. Lee, and S. Cristoloveanu, ?Scaling of SOI FinFlash Memory with Buried Storage ONO Layer?, 2011.

S. Chang, M. Bawedin, W. Xiong, J. Lee, and S. Cristoloveanu, ?Analysis of Hysteresis Effects in FinFETs with ONO Buried Insulator?, 2011.

S. Chang, M. Cheralathan, M. Bawedin, B. Iniquez, B. Bayraktaroglu et al., ?Mobility Model for SOI-like Nanocrystalline Zinc Oxide Thin-Film Transistor?, EuroSOI 2012 Conference, 2012.